Intel Xeon SoC Structural Design Intern - Undergraduate in Hudson, Massachusetts
In this internship, you will be working alongside a world-class SOC design team within the Xeon Engineering Group (XEG) delivering on next-generation Xeon products/IPs for Server markets.
Your responsibilities will include but not be limited to:
Block-level floor planning
Logic synthesis of design blocks
Formal Equivalence Verification FEV
Auto Place-and-Route APR using Synopsys ICC tools
Timing verification using Synopsys PrimeTime as well as Intel tools
Layout vs. Schematic LVS, Design Rule Checks DRC, Electrical Rule Checks ERC, and Design for Manufacturability checks DFM
Assist in the preparation of the layout design database for introduction to manufacturing
Willingness to commit to a 6-9 month internship.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.
This position is not eligible for employment-based visa/immigration sponsorship. Intel sponsors individuals for employment-based visas for positions where we experience a shortage of US Workers. These skills shortage roles are typically STEM contributing positions requiring a Master's or PhD degree, or a Bachelor’s degree with three years’ related job experience. This position does not qualify for Intel Sponsorship because it is either (1) a non-STEM contributing position, or (2) a STEM position that only requires a Bachelor’s degree and less than three years’ experience.
Candidate must be pursuing a Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
3+ months experience with:
CMOS transistor level circuit fundamentals
VLSI hardware design and programming.
Availability for a 6- 9 month (full-time) internship
RTL/Logic design Verilog, VCS, etc.
Electronic Design Automation tools, flows and methodology
ICCDP, Design Compiler, IC Compiler/ICC, Primetime, VCS, Verilog
Layout cleanup expertise DRCs, density, ipc, etc.
TCL, Perl and/or C++ programming
Inside this Business Group
Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.
Virtual US and Canada
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Annual Salary Range for jobs which could be performed in US, Colorado:
$52,000.00-$147,000.00 (Hourly Role)
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here (https://www.intel.com/content/www/us/en/jobs/benefits.html)
Intel is committed to a culture of accessibility. Intel provides accommodations to applicants and employees with disabilities. Find information and request accommodation here (https://jobs.intel.com/page/show/candidate-help-desk)
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